Many integrated circuits have circuit blocks that use different supply voltages. For example, the core logic of an integrated circuit may be designed to operate using a relatively low voltage, e.g., 1.1V, while logic in a charge pump may operate using a relatively high voltage, e.g., 1.8V. In order to reduce the system complexity, the number of power supplies used to provide the different voltages may be minimized by using level shifter circuits. The difficulty of level shifting from a lower supply voltage to a higher supply voltage increases as the frequency of operation increases, especially at operating data rates of 6.5 Gbps (Gigabits per second) and above.
Ideally, a level shifter circuit should have high bandwidth as well as low power consumption. Current level shifter implementations use a mixture of thin gate oxide transistors and thick gate oxide transistors. One skilled in the art will appreciate thick gate oxide transistors are inherently slower and have lower current than a similarly sized thin gate oxide transistor. As a consequence, many of level shifter circuit implementations are performance limited by the use of thick gate oxide transistors to drive the required load at high frequency. For this reason, the thick gate oxide transistors in the level shifter circuit need to be sized larger than if thin gate transistors were used to provide the amount of current needed achieve the frequency of operation, while keeping the load the same. Additionally, the use of larger sized, thick gate oxide transistors limits the performance of the level shifter circuit because the thick gate oxide transistors lead to high capacitive loading and thus lower bandwidth. Additionally, the use of thick gate oxide transistors leads to larger amounts of current and therefore higher power consumption.
It is in this context that embodiments of the invention arise.